Huawei Unveils Tau Scaling Law, Aiming for 1.4-nm-Class Chips by 2031

Chipmakers have periodically rewritten the rulebook when physical limits loomed—Bell Labs’ planar transistor in 1959 and Intel’s transition to copper interconnects in 1997 each extended device scaling when earlier methods plateaued. Huawei’s Tau Scaling Law echoes those pivots, shifting the metric of progress from geometry to signal-delay, much as IBM’s 2004 ‘Power Law’ for multicore design moved emphasis from clock speed to parallelism. Strategically, the move reflects a decades-long pattern of technology-power realignments: Japan’s DRAM leap in the 1980s, South Korea’s foundry rise after the 1997 crisis, and now China’s push after the 2019-2023 U.S. sanctions. Whether Tau succeeds technically, the announcement underscores an irreversible trend toward techno-sovereignty, alternative design paradigms, and vertically integrated national ecosystems. On a 100-year horizon, if time-domain scaling proves viable, the centre of gravity in semiconductor innovation could tilt eastward; if not, this event may be remembered like the Soviet Union’s 1985 ‘Elbrus-3’—ambitious, groundbreaking on paper, but ultimately sidelined by manufacturing realities.